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| LS5911 LS5912 LS5912C Linear Integrated Systems FEATURES Improved Replacement for SILICONIX, FAIRCHILD, & NATIONAL: 2N5911 & 2N5912 LOW NOISE (10kHz) en ~ 4nV/Hz HIGH TRANSCONDUCTANCE (100MHz) ABSOLUTE MAXIMUM RATINGS @ 25 C (unless otherwise stated) Maximum Temperatures Storage Temperature Operating Junction Temperature Maximum Power Dissipation Continuous Power Dissipation (Total) Maximum Currents Gate Current Maximum Voltages Gate to Drain Gate to Source -25V -25V 50mA 500mW S1 D1 SS G1 1 2 3 4 IMPROVED LOW NOISE WIDEBAND MONOLITHIC DUAL N-CHANNEL JFET TO-71 BOTTOM VIEW TO-78 BOTTOM VIEW G1 D1 S1 SOT-23 TOP VIEW 1 2 3 6 5 4 gfs 4000S 1 G1 D1 S1 2 3 5 6 S2 D2 G2 PDIP-A G1 D1 S1 2 3 5 6 S2 D2 G2 S2 D2 G2 1 7 1 7 PDIP-B 8 7 6 5 -65 to +150 C -55 to +150 C S1 D1 SS G1 1 2 3 4 G2 SS D2 S2 S1 D1 G1 NC 1 2 3 4 8 7 6 5 NC G2 D2 S2 SOIC-A 8 7 6 5 SOIC-B G2 SS D2 S2 S1 D1 G1 NC 1 2 3 4 8 7 6 5 NC G2 D2 S2 MATCHING ELECTRICAL CHARACTERISTICS @25 C (unless otherwise stated) SYMBOL CHARACTERISTIC TYP LS5911 MIN MAX LS5912 MIN MAX LS5912C MIN MAX UNIT CONDITIONS VGS1 - VGS2 VGS1 - VGS2 T IDSS1 IDSS2 Differential Gate to Source Cutoff Voltage Differential Gate to Source Cutoff Voltage Change with Temperature Gate to Source Saturation Current Ratio Differential Gate Current Forward Transconductance Ratio2 Common Mode Rejection Ratio 85 10 20 0.95 1 20 0.95 1 0.95 0.95 15 40 1 20 1 0.95 0.95 40 40 1 20 1 mV V/C % nA % dB VDG = 10V, ID = 5mA VDG = 10V, ID = 5mA TA = -55 to +125C VDS = 10V, VGS = 0V VDG = 10V, ID = 5mA TA = +125C VDS = 10V, ID = 5mA f = 1kHz VDG = 5V to 10V ID = 5mA IG1 - IG2 gfs1 gfs2 CMRR STATIC ELECTRICAL CHARACTERISTICS @25 C (unless otherwise stated) SYM. BVGSS VGS(off) VGS(F) VGS IDSS IGSS IG CHARACTERISTIC Gate to Source Breakdown Voltage Gate to Source Cutoff Voltage Gate to Source Forward Voltage Gate to Source Voltage Drain to Source Saturation Current3 Gate Leakage Current Gate Operating Current -1 -1 0.7 -0.3 7 -4 40 -50 -50 -0.3 7 -4 40 -50 -50 -0.3 7 -4 40 -50 -50 mA pA TYP LS5911 MIN -25 -1 -5 MAX LS5912 MIN -25 -1 -5 MAX LS5912C MIN -25 -1 -5 V MAX UNIT CONDITIONS IG = -1A, VDS = 0V VDS = 10V, ID = 1nA IG = 1mA, VDS = 0V VDG = 10V, IG = 5mA VDS = 10V, VGS = 0V VGS = -15V, VDS = 0V VDG = 10V, ID = 5mA Linear Integrated Systems * 4042 Clipper Court * Fremont, CA 94538 * Tel: 510 490-9160 * Fax: 510 353-0261 DYNAMIC ELECTRICAL CHARACTERISTICS @25 C (unless otherwise stated) SYM. CHARACTERISTIC TYP f = 1kHz f = 100MHz f = 1kHz f = 100MHz LS5911 MIN MAX LS5912 MIN MAX LS5912C MIN MAX UNIT CONDITIONS gfs gos Ciss Crss NF en Forward Transconductance Output Conductance Input Capacitance 4000 10000 4000 10000 4000 10000 4000 10000 4000 10000 4000 10000 100 150 5 1.2 1 100 150 5 1.2 1 20 10 100 150 5 1.2 1 20 10 pF dB nV/Hz nV/Hz S VDG = 10V, ID = 5mA Reverse Transfer Capacitance Noise Figure Equivalent Input Noise Voltage f = 100Hz f = 10kHz VDG = 10V, ID = 5mA f = 1MHz VDG = 10V, ID = 5mA f = 10kHz, RG = 100K VDG = 10V, ID = 5mA f = 100Hz VDG = 10V, ID = 5mA f = 10kHz 7 4 20 10 SOT-23 0.95 TO-71 Six Lead 0.35 0.50 2.80 3.00 TO-78 0.230 DIA. 0.209 PDIP 0.060 1 2 8 7 0.375 3 4 6 5 0.100 1 1.90 6 0.195 DIA. 0.175 0.030 MAX. 0.305 0.335 0.335 0.370 2 5 4 0.150 0.115 3 1.50 1.75 2.60 3.00 0.016 0.019 DIM. A 0.016 0.021 DIM. B 0.200 0.029 0.045 23 5 1 76 MAX. 0.040 0.165 0.038 0.185 MIN. 0.500 0.250 6 LEADS 0.019 DIA. 0.016 0.100 0.500 MIN. SEATING PLANE 0.90 1.30 0.100 0.145 0.170 0.050 0.09 0.20 0.295 0.320 DIMENSIONS IN INCHES 23 1 5 6 7 0.100 45 0.00 0.15 0.10 0.60 45 0.046 0.036 SOIC 0.014 0.018 1 2 0.021 3 4 0.150 0.157 8 7 6 5 0.050 0.189 0.196 DIMENSIONS IN MILLIMETERS 0.048 0.028 0.028 0.034 PDIP-A S1 D1 SS G1 1 2 3 4 8 7 6 5 PDIP-B G2 SS D2 S2 S1 D1 G1 NC 1 2 3 4 8 7 6 5 NC G2 D2 S2 0.0040 0.0098 0.2284 0.2440 DIMENSIONS IN INCHES SOIC-A S1 D1 SS G1 1 2 3 4 8 7 6 5 SOIC-B G2 SS D2 S2 0.0075 0.0098 S1 D1 G1 NC 1 2 3 4 8 7 6 5 NC G2 D2 S2 Please contact the factory regarding the availability of optional packages. 1. 2. 3. Absolute maximum ratings are limiting values above which serviceability may be impaired. Pulse Test: PW 300s Duty Cycle 3% Assumes smaller value in numerator. Information furnished by Linear Integrated Systems is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems. Linear Integrated Systems * 4042 Clipper Court * Fremont, CA 94538 * Tel: 510 490-9160 * Fax: 510 353-0261 This datasheet has been download from: www..com Datasheets for electronics components. |
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